1. Technical Field
The present invention relates to a MOS capacitor, a method of fabricating the same, and a semiconductor device using the same, and more particularly, to a technology of using a dummy cell as a MOS capacitor in a semiconductor device employing an open bit line structure.
2. Related Art
Cost savings is an important factor in dynamic random access memories (DRAMs), and shrinkage in chip size is effective in saving costs.
Until now, memory cell sizes have been shrunk through miniaturization process technology, but there is a further need to shrink the chip size by changing a memory arrangement.
In particular, a scheme of arranging a memory cell, which includes one transistor and one capacitor, and a sense amplifier configured to sense and amplify data of the memory cell, is an essential design factor which affects the chip size of the DRAMs. Schemes of arranging a memory cell array including a plurality of memory cell blocks (or a plurality of memory cell mats) and sense amplifiers, include a folded bit line scheme and an open bit line scheme.
Since, in the folded bit line scheme, one sense amplifier is arranged in pitches of four bit lines, a layout design of the sense amplifier is easier than that of the open bit line scheme. However, since the folded bit line scheme requires a memory cell area that is two times greater than that of the open bit line scheme, the chip size increases.
According to the open bit line scheme, memory cells are arranged in all intersections of word lines and bit lines so that a density of the memory cells is highest and thus a small-sized chip can be obtained. However, a bit line and a complementary bit line, which are connected to different memory cell blocks, are connected to a sense amplifier block in the open bit line scheme. That is, one sense amplifier block is arranged in pitches of two bit lines in a sense amplifier arrangement design.
In an open bit line type memory cell array, as a sense amplifier is connected to bit lines coupled to different memory cell blocks, half of the bit lines in the outermost memory cell block remain in a dummy state. That is, dummy cells, which are coupled to the bit lines in the dummy state and thus cannot act as memory cells, are arranged in the outermost memory cell block. As a result, an unnecessary overhead occurs in connection with the chip size.